View CY62157DV30_385370.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY62157DV30 MoBL(R)
8-Mbit (512K x 16) MoBL Static RAM
Features
* Temperature Ranges -- Industrial: -40C to 85C -- Automotive: -40C to 125C (Preliminary) * Very high speed: 45 ns, 55 ns and 70 ns * Wide voltage range: 2.20V - 3.60V * Pin-compatible with CY62157CV25, CY62157CV30, and CY62157CV33 * Ultra-low active power -- Typical active current: 1.5 mA @ f = 1 MHz -- Typical active current: 12 mA @ f = fmax * Ultra-low standby power * Easy memory expansion with CE1, CE2, and OE features * Automatic power-down when deselected * CMOS for optimum speed/power * Packages offered: 48-ball BGA, 48-pin TSOPI, and 44-pin TSOPII
Functional Description[1]
The CY62157DV30 is a high-performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL(R)) in portable applications such as cellular telephones.The device also has an automatic power-down feature that significantly reduces power consumption. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table for a complete description of read and write modes.
Logic Block Diagram
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER
DATA-IN DRIVERS
512K x 16 RAM Array
SENSE AMPS
I/O0 - I/O7 I/O8 - I/O15
COLUMN DECODER
BHE WE OE BLE
A11 A12 A13 A14 A15 A16 A17 A18
CE2
CE1
Power-down Circuit
Notes: 1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, which is available at http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05392 Rev. *E
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised August 24, 2004
CY62157DV30 MoBL(R)
Product Portfolio
Power Dissipation Operating ICC, (mA) VCC Range (V) Product CY62157DV30L CY62157DV30L Range Industrial Automotive[3] Min. 2.2 2.2 2.2 Typ.[2] 3.0 3.0 3.0 Max. 3.6 3.6 3.6 FBGA e
4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11 6 CE2 I/O0 I/O2 Vcc Vss I/O6 I/O7 NC A B C D E F G H
Speed (ns) 45, 55, 70 45, 55, 70 55
f = 1MHz Typ.[2] 1.5 1.5 1.5 Max. 3 3 3
f = fmax Typ.[2] 12 12 12 Max. 20 15 20
Standby ISB2, (A) Typ.[2] 2 2 2 Max. 20 8 50
CY62157DV30LL Industrial
Pin Configuration[4, 5, 6, 7]
op 1 BLE I/O8 I/O9 VSS VCC 2 OE BHE I/O10 I/O11 3 A0 A3 A5 A17
I/O12 DNU A14 A12 A9
I/O14 I/O13 I/O15 A18 NC A8
48TSOPI
Top View
44 TSOP II
Top View
A15 A14 A13 A12 A11 A10 A9 A8 NC DNU WE CE2 DNU BHE BLE A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 BYTE Vss I/O15/A19 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 Vcc I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE Vss CE1 A0
A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A18 A17 A16 A15 A14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 A8 A9 A10 A11 A12 A13
Notes: 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C. 3. Automotive data is PRELIMINARY. Shaded areas of the datasheet contain PRELIMINARY information. 4. NC pins are not internally connected on the die. 5. DNU pins have to be left floating. 6. The BYTE pin in the 48-TSOPI package has to be tied HIGH to use the device as a 512K x 16 SRAM. The 48-TSOPI package can also be used as a 1M x 8 SRAM by tying the BYTE signal LOW. For 1M x 8 Functionality, please refer to the CY62158DV30 datasheet. In the 1M x 8 configuration, Pin 45 is A19. 7. The 44-TSOPII package device has only one chip enable pin (CE).
Document #: 38-05392 Rev. *E
Page 2 of 12
CY62157DV30 MoBL(R)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied............................................ -55C to + 125C Supply Voltage to Ground Potential ......................................... -0.3V to + VCC(max) + 0.3V DC Voltage Applied to Outputs in High-Z State[8, 9] ............................ -0.3V to VCC(max) + 0.3V DC Input Voltage[8, 9] ........................-0.3V to VCC(max) + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA
Operating Range
Device CY62157DV30L CY62157DV30LL CY62157DV30L Automotive -40C to +125C (Preliminary) Range Industrial Ambient Temperature (TA) VCC[10] -40C to +85C 2.20V to 3.60V
Electrical Characteristics Over the Operating Range
CY62157DV30 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current IOH = -0.1 mA IOH = -1.0 mA IOL = 0.1 mA IOL = 2.1mA VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V GND < VI < VCC Industrial Automotive Output Leakage Current GND < VO < VCC, Output Disabled VCC Operating Supply Current f = fMAX = 1/tRC f = 1 MHz ISB1 Automatic CE Power-Down Current -- CMOS Inputs CE1 > VCC-0.2V, CE2< 0.2V Industrial VIN>VCC-0.2V, VIN<0.2V) f = fMAX (Address and Data Automotive Only), f = 0 (OE, WE, BHE and BLE), VCC=3.60V CE1 > VCC - 0.2V or CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V Industrial Automotive Industrial Automotive VCC = VCCmax L IOUT = 0 mA LL CMOS levels L LL L LL L 2 2 Test Conditions VCC = 2.20V VCC = 2.70V VCC = 2.20V VCC = 2.70V 1.8 2.2 -0.3 -0.3 -1 -4 -1 -4 12 Min. 2.0 2.4 0.4 0.4 VCC + 0.3V VCC + 0.3V 0.6 0.8 +1 +4 +1 +4 20 15 1.5 3 3 20 8 50 Typ.[2] Max. Unit V V V V V V V V A A A A mA mA mA mA A
ISB2
Automatic CE Power-Down Current -- CMOS Inputs
L LL L
2 2
20 8 50
A
Notes: 8. VIL(min.) = -2.0V for pulse durations less than 20 ns. 9. VIH(max)= VCC+0.75V for pulse duration less than 20 ns. 10. Full device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 200 s wait time after Vcc stabilization.
Document #: 38-05392 Rev. *E
Page 3 of 12
CY62157DV30 MoBL(R)
Capacitance[11, 12]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max. 10 10 Unit pF pF
Thermal Resistance[11]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board BGA 72 8.86 TSOP II 75.13 8.95 TSOP I 74.88 8.6 Unit C/W C/W
AC Test Loads and Waveforms[13]
VCC OUTPUT
30 pF / 50 pF
R1
VCC GND R2 10%
ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
Rise Time = 1 V/ns
INCLUDING JIG AND SCOPE
Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V
Parameters R1 R2 RTH VTH
2.50V 16667 15385 8000 1.20
3.0V 1103 1554 645 1.75
Unit V
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC= 1.5V CE1 > VCC - 0.2V, CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V Industrial (L) Industrial (LL) Automotive (L) 0 tRC Conditions Min. 1.5 10 4 25 ns ns Typ.[2] Max. Unit V A
tCDR[11] tR[14]
Chip Deselect to Data Retention Time Operation Recovery Time
Notes: 11. Tested initially and after any design or process changes that may affect these parameters. 12. The input capacitance on the CE2 pin of the FBGA and 48TSOPI packages and on the BHE pin of the 44TSOPII package is 15 pF. 13. Test condition for the 45 ns part is a load capacitance of 30 pF. 14. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 us or stable at VCC(min.) > 100 us.
Document #: 38-05392 Rev. *E
Page 4 of 12
CY62157DV30 MoBL(R)
Data Retention Waveform[15]
VCC
CE1 or BHE.BLE
VCC, min. tCDR
DATA RETENTION MODE VDR > 1.5 V
VCC, min. tR
or CE2
Switching Characteristics Over the Operating Range [16]
45 ns [13] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle[19] tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width BLE / BHE LOW to Write End Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[17, 18] WE HIGH to Low-Z[17] 10 45 40 40 0 0 35 40 25 0 15 10 55 40 40 0 0 40 40 25 0 20 10 70 60 60 0 0 45 60 30 0 25 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to LOW Z[17] OE HIGH to High Z[17, 18] CE1 LOW and CE2 HIGH to Low Z[17] CE1 HIGH and CE2 LOW to High Z[17, 18] 0 45 45 10 15 10 20 CE1 LOW and CE2 HIGH to Power-Up CE1 HIGH and CE2 LOW to Power-Down BLE / BHE LOW to Data Valid BLE / BHE LOW to Low Z[17] BLE / BHE HIGH to HIGH Z[17, 18] 10 20 0 55 55 10 25 5 15 10 20 0 70 70 10 45 25 5 20 10 25 45 45 10 55 25 5 25 55 55 10 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 55 ns Min. Max. 70 ns Min. Max. Unit
Notes: 15. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. 16. Test conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" section. 17. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedence state. 19. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05392 Rev. *E
Page 5 of 12
CY62157DV30 MoBL(R)
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[20, 21] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle 2 (OE Controlled) [21, 22] ADDRESS tRC
CE1
tPD tHZCE tACE
CE2
BHE/BLE
tLZBE
OE
tDBE
tHZBE
DATA OUT
tDOE tLZOE HIGH IMPEDANCE tLZCE tPU
tHZOE HIGH IMPEDANCE ICC ISB
DATA VALID
SUPPLY CURRENT
50%
50%
Notes: 20. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. 21. WE is HIGH for read cycle. 22. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document #: 38-05392 Rev. *E
Page 6 of 12
CY62157DV30 MoBL(R)
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled) [19, 23, 24, 25] ADDRESS tSCE
CE1
tWC
CE2 tAW tSA
WE
tHA tPWE
BHE/BLE
tBW
OE
tSD DATA I/O
See note 24
tHD
VALID DATA tHZOE
Write Cycle 2 (CE1 or CE2 Controlled) [19, 23, 24, 25]
tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE WE tBW tHA
BHE/BLE
OE tSD DATA I/O
See note 24
tHD
VALID DATA tHZOE
Notes: 23. Data I/O is high impedance if OE = VIH. 24. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state. 25. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05392 Rev. *E
Page 7 of 12
CY62157DV30 MoBL(R)
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW)
[24, 25]
tWC ADDRESS tSCE
CE1
CE2
BHE/BLE
tBW tAW tSA tPWE tHA
WE
tSD DATA I/O
See note 24
tHD
VALID DATA tHZWE tLZWE
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[24, 25] tWC ADDRESS CE1 CE2
tSCE tAW tBW tSA
tHA
BHE/BLE
WE
tPWE tSD tHD
DATA I/O
See note 24
VALID DATA
Document #: 38-05392 Rev. *E
Page 8 of 12
CY62157DV30 MoBL(R)
Truth Table
CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H H L L L L H Inputs/Outputs High Z High Z High Z Mode Deselect/Power-Down Deselect/Power-Down Deselect/Power-Down Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Data Out (I/O0 - I/O15) Read (Upper byte and Lower Byte) Data Out (I/O0 - I/O7); Read (Lower Byte only) High Z (I/O8 - I/O15) High Z (I/O0 - I/O7); Read (Upper Byte only) Data Out (I/O8 - I/O15) High Z High Z High Z Data In (I/O0 - I/O15) Data In (I/O0 - I/O7); High Z (I/O8 - I/O15) High Z (I/O0 - I/O7); Data In (I/O8 - I/O15) Output Disabled Output Disabled Output Disabled Write(Upper byte and Lower Byte) Write (Lower Byte only) Write (Upper Byte only)
Ordering Information
Speed (ns) 45 45 45 55 55 55 55 55 55 55 55 70 70 70 Ordering Code CY62157DV30L-45BVI CY62157DV30LL-45BVI CY62157DV30L-45ZXI CY62157DV30LL-45ZXI CY62157DV30L-45ZSXI CY62157DV30LL-45ZSXI CY62157DV30L-55BVI CY62157DV30LL-55BVI CY62157DV30L-55BVXI CY62157DV30LL-55BVXI CY62157DV30L-55BVE CY62157DV30L-55ZXI CY62157DV30LL-55ZXI CY62157DV30L-55ZXE CY62157DV30L-55ZSXI CY62157DV30LL-55ZSXI CY62157DV30L-55ZSXE CY62157DV30L-55ZSI CY62157DV30LL-55ZSI CY62157DV30L-70BVI CY62157DV30LL-70BVI CY62157DV30L-70BVXI CY62157DV30LL-70BVXI CY62157DV30L-70ZXI CY62157DV30LL-70ZXI Package Name Package Type BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Z-48 ZS-44 BV48A BV48A BV48A Z-48 Z-48 ZS-44 ZS-44 ZS-44 BV48A BV48A Z-48 48-pin TSOP I (Pb-free) 44-pin TSOP II (Pb-free) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-free) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 48-pin TSOP I (Pb-free) 48-pin TSOP I (Pb-free) 44-pin TSOP II (Pb-free) 44-pin TSOP II (Pb-free) 44-pin TSOP II 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) (Pb-free) 48-pin TSOP I (Pb-free) Operating Range Industrial Industrial Industrial Industrial Industrial Automotive Industrial Automotive Industrial Automotive Industrial Industrial Industrial Industrial
Document #: 38-05392 Rev. *E
Page 9 of 12
CY62157DV30 MoBL(R)
Ordering Information (continued)
Speed (ns) 70 70 Ordering Code CY62157DV30L-70ZSXI CY62157DV30LL-70ZSXI CY62157DV30L-70ZSI CY62157DV30LL-70ZSI Package Name Package Type ZS-44 44-pin TSOP II (Pb-free) ZS-44 44-pin TSOP II Operating Range Industrial Industrial
Package Diagrams
48-ball (6.0 mm x 8.0 mm x 1.0 mm) Fine Pitch BGA BV48A
51-85150-*B
Document #: 38-05392 Rev. *E
Page 10 of 12
CY62157DV30 MoBL(R)
Package Diagrams (continued)
DIMENSIONS IN INCHES[MM] MIN. JEDEC # MO-142
48-Lead TSOP I (12 mm x 18.4 mm x 1.0 mm) Z48A
MAX. 0.037[0.95] 0.041[1.05]
N
1
0.020[0.50] TYP.
0.472[12.00]
0.007[0.17] 0.011[0.27]
0.724 [18.40] 0.047[1.20] MAX. 0.787[20.00] SEATING PLANE 0.004[0.10] 0.004[0.10] 0.008[0.21] 0.020[0.50] 0.028[0.70] 0.010[0.25] GAUGE PLANE 0-5
0.002[0.05] 0.006[0.15]
51-85183-*A
44-Pin TSOP II ZS44
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05392 Rev. *E
Page 11 of 12
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62157DV30 MoBL(R)
Document History Page
Document Title:CY62157DV30 MoBL(R) 8-Mbit (512K x 16) MoBL Static RAM Document Number: 38-05392 REV. ** *A *B *C ECN NO. Issue Date 126316 131013 133115 211601 05/22/03 11/19/03 01/24/04 See ECN Orig. of Change HRT CBD AJU Description of Change New Data Sheet Minor Change: Change MPN and upload. Change from Preliminary to Final Changed Marketing part number from CY62157DV to CY62157DV30 in the title and in the Ordering Information table Added footnotes 4, 5 and 11 Modified footnote 8 to include ramp time and wait time Removed MAX value for VDR on Data Retention Characteristics table Changed ordering code for Pb-free parts Modified voltage limits in Maximum Ratings section
CBD/LDZ Change from Advance to Preliminary
*D *E
236628 257349
See ECN See ECN
SYT/AJU Added 45-ns and 70-ns Speed Bins Added Automotive product information PCI Added test condition for 45 ns part (footnote #13 on page 4)
Document #: 38-05392 Rev. *E
Page 12 of 12

▲Up To Search▲

Price & Availability of CY62157DV30

	To Download CY62157DV30 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .